Like everything else about the AS/400, memory management is a multilevel concept: OS/400 sees only objects, which it identifies by name and type; the Technology Independent Machine Interface (MI) sees Objects and their pointers; the System Licensed Internal Code (SLIC) sees a single 64-bit addressable virtual memory space addressed by the pointers: the Single-Level Store; but the hardware has to deal with the traditional memory hierarchy of registers, cache, main memory, disk drives, tape drives, etc., just like any other computer.

The AS/400 is an object based system. All operating system and application programs operate on and are objects. However, objects appear differently at each level. OS/400 objects may consist of one or more MI system objects. OS/400 keeps track of which system objects are included in an OS/400 object and SLIC manages the system objects. For example, an OS/400 object might be a database file which would consist of several system objects such as a space, a data space, a data space index and a cursor.

Objects are containers which hold other objects and more primitive structures. As such objects are a basic unit for the allocation of memory. Each object is allocated at least one, and generally two or more, 16 megabyte segments of virtual memory space. Each object consists of a functional portion and a space portion which are stored in separate segments. There is a system object called a space, which has no functional portion and can therefore consist of a single segment. Most objects consist of a base segment and one or more secondary segments.

Each segment contains a segment header which contains information on the segment type, whether it is temporary or permanent, whether or not additional pages can be allocated as required, whether or not the segment contains system pointers, the number of pages allocated to the segment, the location of the base segment and the location of the next secondary segment. Segment types include MI observable types such as base or various types of secondary segments and SLIC only segments.

Above the MI, access to an object requires the object name, type and subtype. This is called the symbolic address. At the MI these are resolved into a system pointer of 16 bytes. The system pointer contains the 64-bit virtual address of the object plus other information such as the pointer type, the object type and authority for system state operations - user state authority is stored elsewhere. There is also room to expand the address to 96 bits in future implementations.

On the AS/400, system pointers may be used but not manipulated. Because pointers are stored in user accessible space, they represent a security hazard (this is also why user- state authority is not stored in the pointer). In order to protect pointers from user manipulation, they are designed so that a user changed pointer becomes invalid. Each pointer has an associated tag bit stored in a separate, user inaccessible area of memory. Modification of the pointer by any instruction other than a limited number of privileged, SLIC-only instructions will reset the tag-bit.

System objects may be designated as temporary or permanent. Permanent objects exist until they are explicitly destroyed. Even when explicitly destroyed, the virtual address of a permanent object is never reused. This prevents the accidental (or intentional) use of a pointer to a destroyed object to access a new object. Temporary objects are destroyed at Initial Program Load (IPL).

Single-Level Store.

Single-level store is IBM’s term for the AS/400 implementation of virtual memory. Single-level describes its representation of all types of memory objects within a single 64-bit address virtual memory space. The single-level store is located entirely within the System Licensed Internal Code (SLIC).

The more normal approach to virtual memory is a two-level store in which the programmer deals with separate storage for memory and file system. Of course, since the single-level store is located below the MI, the ordinary applications programmer sees all of this by implication rather than directly. In fact, the applications programmer does have to deal with a file system, but it is built on objects rather than traditional concepts of memory and files.

One implication of the single-level store concept is that the effective address and the virtual address are the same. There are three exceptions to this: user programs running under C-2 level security, Effective Addresses beginning with $800 and Effective Addresses beginning with $801. The normal EA consists of a 40-bit Segment ID and a 24-bit offset (12-bits page and 12-bits byte). In the Virtual Address, the 40-bit Segment ID is combined with the 12-bit page offset to form the 52 bit Virtual Page Number (VPN).

The PowerPC provides a segment table for translating Effective Addresses into virtual addresses. The AS/400 does not normally use this. However, when running under C-2 level security there is a requirement for OS/400 to audit access to objects. By forcing translations to go through the segment table, OS/400 can meet this requirement. There is a performance penalty for this translation, and it applies only to programs in user mode, not to OS/400 programs.

Effective Addresses beginning with $800 translate directly to real addresses, i.e., the least significant 52 bits are the real address.

Effective Addresses beginning with $801 map the I/O space. This provides over 256 million segments for I/O addressing. (Precisely 2²⁸ segments.)

Before performing a page table lookup the hardware will first check the Translation Lookaside Buffer to see if the page has been referenced recently. This step will usually resolve over 95 percent of the page references and is much faster than a page table search.

When the TLB fails to provide a target page frame, the AS/400 uses an inverted page table to locate the physical page frame associated with a VPN. An index key to the page table is created by applying a hashing algorithm to the VPN. This key points to a page table entry group (PTEG) of eight pages. If the virtual page is not located a page fault occurs. (Actually there may be a search of a secondary Page table if there are more than eight pages with the same key.)

A successful search of the page table yields a Page Table Entry (PTE). The PTE is 16 bytes long. The first 57 bits of the PTE constitute the Abbreviated Virtual Page Number (AVPN). (It is abbreviated with respect to the PowerPC’s 80-bit virtual address, not the AS/400’s 52 bit VPN.) A match occurs if the least significant 52 bits of the AVPN match the VPN and the PTE’s Valid bit is equal to 1. In this case the PTE contains a 40-bit Real Page Number (RPN) which is the location of the page frame in physical memory containing the virtual page being sought.

In the case of a page fault, the necessary page must be retrieved from disk. Generally this also means that a page currently residing in physical memory will have to be removed. The policy for selecting the page to be removed is a variant of the Least Recently Used (LRU) policy called the enhanced second chance algorithm (Silberschatz and Galvin, p. 323). The PTE provides fields to support this policy: a Reference bit (R) and a Change bit (C). The memory manager looks for a page with R=0 and C=0 meaning it has neither been referenced or changed recently. This minimizes the processing required to swap the page out. While conducting the search for a page to replace, the memory manager builds a list of changed pages that have not been recently referenced. When this list reaches a critical length, the memory manager initiates a process to write out the changed pages (and thereby reset the Change bit). This helps to insure that there are R=0/C=0 pages available for replacement. After a page fault, all R-bits are reset to 0.

The PTE also provides fields to govern the memory access mode:

Write-Through mode insures than main memory is current, which can be important to correct operation of multiple processor systems. On the other hand, turning Write- Through mode off reduces the overhead on individual writes.

Inhibiting caching during long sequential reads can prevent the cache from being flushed of data more likely to be used again. This will improve overall cache performance.

Memory Coherence enforces strict write order when the memory manager might do otherwise to optimize operations. This supports the requirements of multiple processor systems for serialization of operations.

Guarded Storage disables speculative execution of instructions by the processor pipelines.

The most obvious difference between the single-level store and traditional memory management is in the organization and management of disk storage. Traditionally this falls under the purview of a separate and distinct file system. Under single-level store, the definition of a file is narrowed considerably, but files are only one of many types of objects stored on disk. Primary access to disk storage is via directories which locate segments rather than files and segments are identified by their virtual address.

On the AS/400 disk space is known as auxiliary storage and is controlled by auxiliary storage management in the SLIC. Auxiliary storage is divided into sixteen or fewer Auxiliary Storage Pools (ASP) each consisting of one or more disk arms. This subdivision of disk storage is intended to reduce the effort required to restore the system following a disk crash. Each object must be stored on a single ASP and the ASP is the only information available to OS/400 about the location of the object on disk.

Physically, AS/400 disks are divided into sectors containing 512 bytes of data, but the smallest amount allocated is an extent which consists of at least one page, or 8 sectors. An extent is a contiguous set of sectors equal to 2ⁿ pages where n=0,1,2...12. Thus smallest extent will hold one page and the largest will hold a fully allocated segment.